Semiconductor integrated circuits contain many distinct electronic devices having conductive elements as part of the device structure. In order to operate as a circuit, each device needs to be electrically interconnected with other devices. Interconnection occurs during the fabrication process by forming an intricate network of conductive material in contact with certain elements of the devices. For example, part of a semiconductor integrated circuit may be made up of hundreds of discrete field effect transistors having interconnected gate electrodes.
The typical structure of a semiconductor integrated circuit includes a single crystal silicon substrate with doped regions forming the source and the drain of a transistor. The gate electrode is constructed by forming a layer of conductive polycrystalline silicon (polysilicon or simply "poly") above an insulating gate oxide layer. Polysilicon is less conductive than conductive metals, but has various advantages over the metals, such as allowing for a lower threshold voltage and higher density of cells. Since it has a moderately low sheet resistivity, the polysilicon layer can be extended to adjacent devices, thereby providing interconnection, but it is not adequate for interconnection over long distances. Interconnect lines made of polysilicon must have a relatively large cross-section in order to be conductive enough to operate effectively. This in turn increases the size of the overall integrated circuit, reducing speed and flexibility while increasing cost.
If conductivity were the only design criterion, a metal such as silver, aluminum or copper would be the material of choice to form device interconnections. However, many of the processes required in fabricating semiconductor integrated circuits use high temperature levels. Silver and aluminum have relatively low melting points subjecting them and surrounding material to corruption during subsequent fabrication steps. Their relatively high coefficient of thermal expansion as compared to materials such as silicon and silicon dioxide used in the fabrication of other microcircuit elements can cause stress, warping and separation as the metals expand and contract over such materials. Other highly conductive metals such as gold and copper rapidly diffuse through the substrate forming generation sites, thereby reducing minority carrier lifetime and degrading refresh performance in memory devices.
Currently, the methods and structures used for decreasing the sheet resistivity of polysilicon involve tungsten and titanium, which, although less conductive than silver, have a much higher melting point and smaller coefficient of thermal expansion. For example, one such method includes forming a layer of tungsten silicide (WSi.sub.x, where X is any integer greater than or equal to 1, but most commonly 2 or 3 when used in integrated circuits) has been deposited atop the polysilicon layer.
Using titanium instead of tungsten provides greater conductivity, although other problems arise. Titanium silicide (TiSi.sub.x) is formed by first depositing a layer of titanium a top the polysilicon and then applying heat to the layer. The resulting titanium silicide layer can suffer from severe agglomeration problems if the TiSi.sub.x layer is exposed to temperatures greater than 850.degree. C. Since many fabrication processes require high levels of heat, the use of TiSi.sub.x becomes restricted. Other problems with using TiSi.sub.x include unwanted dopant segregation and diffusion of titanium down through the polysilicon in the substrate during heating, which can reduce minority carrier lifetime during operation. In addition, etching TiSi.sub.x is difficult because the layer created is very rough, having non-uniform thickness. This makes it difficult to stop etching the TiSi.sub.x without penetrating into the underlying polysilicon layer. If the titanium is etched prior to its conversion into TiSi.sub.x , the volume change due to thermal expansion and contraction that occurs during conversion may cause cracks or voids to form.
Thus, there is a need for improved structures that increase the conductivity of the device elements and interconnections without the drawbacks described above.